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data sheet ics8543bg revision e december 17, 2010 1 ?2010 integrated device technology, inc. low skew, 1-to-4, differential-to-lvds fanout buffer ics8543 general description the ics8543 is a low skew, high performance 1-to-4 differential-to-lvds clock fanout buffer. utilizing low voltage differential signaling (lvds) the ics8543 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100 ? . the ics8543 has two selectable clock inputs. the clk, nclk pair can accept most standard differential input levels. the pclk, npclk pair ca n accept lvpecl, cml, or sstl input levels. the clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the ics8543 ideal for those applications demanding well defined performance and repeatability. features ? four differential lvds output pairs ? selectable different ial clk, nclk or lvpecl clock inputs ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? pclk, npclk pair can accept the following differential input levels: lvpecl, cml, sstl ? maximum output frequency: 800mhz ? translates any single-ended input signals to lvds levels with resistor bias on nclk input ? additive phase jitter, rms: 0.164ps (typical) ? output skew: 40ps (maximum) ? part-to-part skew: 500ps (maximum) ? propagation delay: 2.6ns (maximum) ? full 3.3v supply mode ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages ics8543 20-lead tssop 6.5mm x 4.4mm x 0.925 mm package body g package top view pin assignment block diagram 0 1 d q le 0 1 q0 nq0 q1 nq1 q2 nq2 q3 nq3 clk_en clk clk_sel oe pulldown pulldown nclk pullup pullup pullup pclk pulldown npclk pullup 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd oe npclk pclk nclk clk clk_sel clk_en gnd v dd q0 nq0 v dd q1 nq1 q2 nq2 gnd q3 nq3
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 2 ?2010 integrated device technology, inc. table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 9, 13 gnd power power supply ground. 2 clk_en input pullup synchronizing clock enable. when high, cl ock outputs follows clock input. when low, qx outputs are forced low, nqx outputs are forced high. lvcmos / lvttl interface levels. 3 clk_sel input pulldown clock select input. when high, selects pclk, npclk inputs. when low, selects clk, nclk inputs. lvcmos / lvttl interface levels. 4 clk input pulldown non-inverting differential clock input. 5 nclk input pullup inverting differential clock input. 6 pclk input pulldown non-inverting differential lvpecl clock input. 7 npclk input pullup inverting differential lvpecl clock input. 8 oe input pullup output enable. controls enabling and disabling of outputs q[0:3], nq[0:3]. lvcmos/lvttl interface levels. 10, 18 v dd power positive supply pins. 11, 12 nq3, q3 output differential out put pair. lvds interface levels. 14, 15 nq2, q2 output differential out put pair. lvds interface levels. 16, 17 nq1, q1 output differential out put pair. lvds interface levels. 19, 20 nq0, q0 output differential out put pair. lvds interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 3 ?2010 integrated device technology, inc. function tables table 3a. control input function table after clk_en switches, the clock outputs are disabled or enab led following a rising and falling input clock edge as shown in fi gure 1. in the active mode, the state of the outpu ts are a function of the clk/nclk and pclk/npclk inputs as described in table 3b. figure 1. clk_en timing diagram table 3b. clock input function table note 1: please refer to the application information section, wiring the differential input to accept single-ended levels. inputs outputs oe clk_en clk_sel selected source q[0:3] nq[0:3] 0 x x hi-z hi-z 1 0 0 clk, nclk disabled; low disabled; high 1 0 1 pclk, npclk disabled; low disabled; high 1 1 0 clk, nclk enabled enabled 1 1 1 pclk, npclk enabled enabled inputs outputs input to output mode polarity clk or pclk nclk or npclk q[0:3] nq[0:3] 0 1 low high differential to differential non-inverting 1 0 high low differential to differential non-inverting 0 biased; note 1 low high single-ended to differential non-inverting 1 biased; note 1 high low single-ended to differential non-inverting biased; note 1 0 high low single- ended to differential inverting biased; note 1 1 low high single-ended to differential inverting enabled disabled clk_en clk, pclk nclk, npclk q0:q3 nq0:nq3
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 4 ?2010 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuos current surge current 10ma 15ma package thermal impedance, ja 73.2 c/w (0 lfpm) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v i dd power supply current 50 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 3.765 v v il input low voltage 0.8 v i ih input high current oe, clk_en v dd = v in = 3.465v 5 a clk_sel v dd = v in = 3.465v 150 a i il input low current oe, clk_en v dd = 3.465v, v in = 0v -150 a clk_sel v dd = 3.465v, v in = 0v -5 a
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 5 ?2010 integrated device technology, inc. table 4c. differential dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . table 4d. lvpecl dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c note 1: common mode input voltage is defined as v ih . table 4e. lvds dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c symbol parameter test conditions minimum typical maximum units i ih input high current clk v dd = v in = 3.465v 150 a nclk v dd = v in = 3.465v 5 a i il input low current clk v dd = 3.465v, v in = 0v -5 a nclk v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 0.5 v dd ? 0.85 v symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk v dd = v in = 3.465v 150 a npclk v dd = v in = 3.465v 5 a i il input low current pclk v dd = 3.465v, v in = 0v -5 a npclk v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage 0.3 1.0 v v cmr common mode input voltage; note 1 1.5 v dd v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 200 280 360 mv ? v od v od magnitude change 0 40 mv v os offset voltage 1.125 1.25 1.375 v ? v os v os magnitude change 5 25 mv i oz high impedance leakage -10 +10 a i off power off leakage -20 1 +20 a i osd differential output short circuit current -3.5 -5 ma i os output short circu it current -3.5 -5 ma v oh output voltage high 1.34 1.6 v v ol output voltage low 0.9 1.06 v
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 6 ?2010 integrated device technology, inc. ac electrical characteristics table 5. ac characteristics, v dd = 3.3v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters measured at 500mhz unless noted otherwise. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differential output cross points. note 3: defined as skew between outputs on different devices oper ating at the same supply voltage, same frequency, same tempera ture and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po ints. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units f max maximum output frequency 800 mhz t pd propagation delay; note 1 ? 800mhz 1.7 2.6 ns t jit buffer additive phase jitter, rms; refer to additive phase jitter section 153.6mhz, integration range: 12khz ? 20mhz 0.164 ps t sk(o) output skew; note 2, 4 40 ps t sk(pp) part-to-part skew; note 3, 4 500 ps t r / t f output rise/fall time 20% to 80% @ 50mhz 150 350 ps odc output duty cycle odc 45 50 55 %
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 7 ?2010 integrated device technology, inc. additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamen tal frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device m eets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. additive phase jitter @ 153.6mhz 12khz to 20mhz = 0.164ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 8 ?2010 integrated device technology, inc. parameter measureme nt information 3.3v lvds output load ac test circuit differential output level part-to-part skew differential input level output skew propagation delay scope qx nqx lvds 3.3v5% power supply +? float gnd v dd v dd gnd v os cross points v od nq[0:3] q[0:3] t sk(pp) part 1 part 2 nqx qx nqy qy v dd gnd nclk, clk, v cmr cross points v pp npclk pclk nqx qx nqy qy t sk(o) clk, pclk t pd nq[0:3] q[0:3] nclk, npclk
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 9 ?2010 integrated device technology, inc. parameter measurement in formation, continued output rise/fall time offset voltage setup high impedance leakage current setup output duty cycle/pulse width/period differential output voltage setup differential output short circuit setup 20% 80% 80% 20% t r t f v od nq[0:3] q[0:3] out out lvds dc input ? ? ? v os / ? v os v dd out out lvds dc inpu t ? ? 3.3v5% power supply float gnd + _ i oz i oz t pw t period t pw t period odc = x 100% nq[0:3] q[0:3] ? ? ? 100 out out lvds dc input v od / ? v od v dd out out lvds dc input ? i osd v dd
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 10 ?2010 integrated device technology, inc. parameter measurement in formation, continued output short circuit current setup power off leakage setup applications information wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration re quires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels out lvds dc input ? i os ? i osb v dd out lvds ? i off v dd
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 11 ?2010 integrated device technology, inc. 3.3v differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of t he driver component to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. clk/nclk input driven by an idt open emitter lvhstl driver figure 3c. clk/nclk input driven by a 3.3v lvpecl driver figure 3e. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver figure 3f. clk/nclk input dri ven by a 2.5v sstl driver r1 50 ? r2 50 ? 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt lvhstl driver differential input r3 125 ? r4 125 ? r1 84 ? r2 84 ? 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl differential input hcsl *r3 33 ? *r4 33 ? clk nclk 3.3v 3.3v zo = 50 ? zo = 50 ? differential input r1 50 ? r2 50 ? *optional ? r3 and r4 can be 0 ? clk nclk differential input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 ? r2 50 ? r2 50 ? 3.3v r1 100 ? lvds clk nclk 3.3v receive r zo = 50 ? zo = 50 ? clk nclk differential input sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 ? r2 120 ? r3 120 ? r4 120 ?
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 12 ?2010 integrated device technology, inc. 3.3v lvpecl clock input interface the pclk/npclk accepts l vpecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4e show interface examples for the pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of t he driver component to confirm the driver termination requirements. figure 4a. pclk/npclk inpu t driven by a cml driver figure 4c. pclk/npclk input driven by a 3.3v lvpecl driver figure 4e. pclk/npclk input driven by a 2.5v sstl driver figure 4b. pclk/npclk input driven by a built-in pullup cml driver figure 4d. pclk/npclk input driven by a 3.3v lvpecl driver with ac couple pclk npclk lvpecl input cml 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v r1 50 ? r2 50 ? r3 125 ? r4 125 ? r1 84 ? r2 84 ? 3.3v zo = 50 ? zo = 50 ? pclk npclk 3.3v 3.3v lvpecl lvpecl input pclk npclk lvpecl input sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 r2 120 r3 120 r4 120 3.3v r1 100 ? cml built-in pullup pclk npclk 3.3v lvpecl input zo = 50 ? zo = 50 ? r1 50 ? r2 50 ? r5 100 ? - 200 ? r6 100 ? - 200 ? pclk vbb npclk 3.3v lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v lvpecl input c1 c2
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 13 ?2010 integrated device technology, inc. recommendations for unused input and output pins inputs: clk/nclk i nputs for applications not requiring the us e of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. pclk/npclk i nputs for applications not requiring the us e of the differential input, both pclk and npclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from pclk to ground. lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvds outputs all unused lvds outputs should be terminated with 100 ? resistor between the differential pair. lvds driver termination a general lvds interface is shown in figure 5. standard termination for lvds type output stru cture requires both a 100 ? parallel resistor at the receiver and a 100 ? differential transmission line environment. in order to avoid any transmission line reflection issues, the 100 ? resistor must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 5 can be used with either type of output structure. if using a non-standard termination, it is recommended to contact idt and conf irm if the output is a current source or a voltage source type structure. in addition, since these outputs are lvds compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. figure 5. typical lvds driver termination 100 ? ? + 100 ? differential transmission line lvds driver lvds receiver
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 14 ?2010 integrated device technology, inc. power considerations this section provides information on power dissipa tion and junction temperature for the ics8543. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8543 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. power (core) max = v dd_max * i dd_max = 3.465v * 50ma = 173.25mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 73.2c/w per table 6 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.173w * 73.2c/w = 82.7c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resitance ja for 20 lead tssop, forced convection ja by velocity linear feet per minute 0200500 single-layer pcb, jedec standard te st boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 15 ?2010 integrated device technology, inc. reliability information table 7. ja vs. air flow table for a 20 lead tssop transistor count the transistor count for ics8543 is: 636 package outline and package dimensions package outline - g suffix for 20 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ja by velocity linear feet per minute 0200500 single-layer pcb, jedec standard te st boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w all dimensions in millimeters symbol minimum maximum n 20 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 16 ?2010 integrated device technology, inc. ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 8543bg ics8543bg 20 lead tssop tube 0 c to 70 c 8543bgt ics8543bg 20 lead tssop 2500 tape & reel 0 c to 70 c 8543bglf ics8543bglf ?lead-free? 20 lead tssop tube 0 c to 70 c 8543bglft ics8543bglf ?lead-free? 20 lead tssop 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ics8543bg revision e december 17, 2010 17 ?2010 integrated device technology, inc. revision history sheet rev table page description of change date a t4e 5 in the v ol row, 1.06 has been moved to the typica l column from the maximum column. 9/18/01 a 3 updated figure 1, clk_en timing diagram. 10/17/01 a 3 updated figure 1, clk_en timing diagram. 11/2/01 a 1 6 - 10 features section, bullet 6 to read 3.3v lvds levels instead of lvpecl. updated parameter measurement information figures. 5/6/02 b t5 5 ac characteristics table - revised output frequency from 650mhz to 800mhz. 6/5/02 c 4e 1 5 features - deleted bullet "designed to meet or exceed the requirements of ansi tia/eia-644". lvds table - changed v od typical value from 350mv to 280mv. 9/19/02 d t2 2 4 9 10 11 pin characteristics - changed c in 4pf max. to 4pf typical. absolute maximum ratings - changed output rating. added differential clock input interface section. added lvpecl clock i nput interface section. added lvds driver termination section. updated format throughout data sheet. 12/31/03 d t1 2 pin description table - added function description to the oe pin. 4/7/04 d t8 10 13 updated lvpecl clock input interface section. added lead free part number to ordering information table. 6/16/04 d 3 10 11 12 13 updated figure 1, clk_en timing diagram. updated differential clock input interface section. updated lvpecl clock input interface section. added recommendation for unused input and output pins section. added power considerations section. updated format throughout the datasheet. 2/27/08 e t5 t9 1 6 7 10 11 12 13 16 features section - added additive phase jitter bullet. ac characteristics table - added add ed phase jitter spec and thermal note. added additive phase jitter plot. updated wiring the differential input to accept single-ended levels section. updated 3.3v differential clock input interface section. updated 3.3v lvpecl clock input interface section. updated lvds driver termination section. ordering information table - deleted ?ics? prefix from part/order number column. updated datasheet header/footer style. 11/12/10 e 1 14 page 1, corrected header title. power considerations - corrected typo for ju nction temperature from 827.7c to 82.7c. 12/17/10
ics8543 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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